1. Field of the Invention
The present invention relates to sense amplifiers and more particularly to a new sense amplifier having a shared equalizer circuit and a timer circuit to prevent the inactive bitlines from floating for long time periods.
2. Description of the Related Art
Integrated circuit memory devices are commonly divided into arrays of memory cells. Usually only one of the arrays is activated during a given access cycle to reduce power consumption and increase the efficiency of the integrated circuit. Because of this operation, a sense amplifier or an array of sense amplifiers are positioned between the memory cell arrays. This allows the sense amplifier to be shared by adjacent arrays, thereby decreasing chip area consumed by the memory device, decrease the production costs and increasing processing speed.
A conventional shared dynamic random access memory (DRAM) sense amplifier (SA) is shown in FIG. 1. The sense amplifier includes equalizer circuits 103, 109 which are supplied with bitline equalization voltages 102, 111. The equalizer circuits 103, 109 are outside the multiplexors 104, 108. Additionally data lines 107 are selected by a column select signal 110. A cross-coupled pair of NFETs 105 and a cross-coupled pair of PFETs 106 are also part of the same sense amplifier and perform the signal sensing and data latching functions of the sense amplifier. The bitlines 100, 101 which are connected to the adjacent arrays are also illustrated. Having two multiplexor (MUX) devices 104, 108 allows the sense amplifier to service two arrays, thus increasing layout efficiency.
During a precharging operation, the sets of bitlines 100, 101 are adjusted to an equalizing potential which is generally midway between the active bitline high potential and the active bitline low potential. During the active phase of the row cycle, one each pair of active bitlines is raised to the active bitline high level and the other is lowered to the active bitline low level. During the precharge phase of the row cycle, these bitlines are connected together and equalized to a voltage midway between the active bitline high and low levels.